COMP2021: Digital System Structures

Laboratory Exercise 3

Combinational design and Simulation with VHDL

1. Goals

  1. Gain experience in combinational design methodology;
  2. Gain an understanding of the design flow and the role of CAD tools in digital design;
  3. Gain an understanding of structural and behavioral VHDL design styles;
  4. Practice hierarchical design techniques;
  5. Practice the implementation of structural and behavioral combinational designs;
  6. Understand the principles and benefits of design simulation.

2. References

Please read the following chapters and sections of the text book carefully and understand the content before attempting the lab exercise.

A. Preparation and Overview

PREPARATION! You are required to prepare for this laboratory by reading Sections A to C of these notes and completing the paper-based design exercises before its commencement. Please ask your demonstrator to check your designs during the lab class. You should file these documents for compilation into a Lab03 Report that will be inspected and marked during Weeks 7 and 8 (refer to the time table on the class web for more details).

You should exercise doing section B, before you attempt section C. Please make sure you understand every bit of the explanation and follow it thoroughly. It is imperative to learn how to use the VMware virtual machine, the Xilinx ISE application, and the ModelSim program, before the remaining lab exercises.

In part C, you will be asked to create an ISE project for Lab03 by following the detailed steps given. A printout of your completed design and a copy of your design file should be kept as part of the Lab03 Report. Synthesise and simulate the design to verify its correctness. Save a copy of the simulation and include a printed copy in your Lab03 Report.

B.Preparation Exercise

B-1. Design problem

There are several ways of representing decimal digits using binary codes. We commonly use the Binary Coded Decimal system or BCD to represent the 10 decimal digits 0-9. This code assigns a different weight to each of 4 bit positions. In order, from the most significant position to the least, these are 8, 4, 2, and 1, corresponding to the 3rd, 2nd, 1st, and 0th powers of 2 respectively.

One of several alternative weighted codes, known as 84-2-1, assigns the weights 8, 4, -2, and -1 respectively to a 4-bit code. A unique bit combination with value equal to its decimal equivalent can thus be formed for each of the 10 decimal digits. These combinations appear listed in the table below.

 

 

 Decimal 

 84-2-1 

 BCD 

 

  ABCD

WXYZ

0

  0000

0000

1

  0111

0001

2

  0110

0010

3

  0101

0011

4

  0100

0100

5

  1011

0101

6

  1010

0110

7

  1001

0111

8

  1000

1000

9

  1111

1001

 

The objective of this exercise is to design, implement, and test a combinational code converter that will output the corresponding 4-bit BCD code for a given 4-bit 84-2-1 input. The design will consist of a minimal two-level circuit for each of the four output bits, W, X, Y, and Z. Each of these circuits will be a function of the four bits representing the BCD input code, A, B, C, and D. Having obtained a design on paper, you will implement your design by describing the circuits using a mixture of behavioral and structural VHDL. The design will then be synthesised and simulated using the ISE CAD tool suite.

B-2. Detailed instructions

1.    Use the Lab 3 Worksheet (PDF File) to obtain a minimal sum of products expression for each of the 84-2-1 code output bits, W, X, Y, and Z in terms of the BCD input bits, A, B, C, and D. Treat unused input combinations as DON'T CARES.

2.    On a blank piece of paper draw a two-level implementation for each of the circuits obtained in Step 1 assuming the inputs are available both in complemented and un-complemented forms.

3.    Start a VMware session (PDF File) and map your Unix Home to drive letter E:. NOTE: You should save your work to a folder/directory on E: so that you do not lose it. Work saved to the C: drive is lost as soon as you close your VMware session. These notes assume you are saving your project to the folder E:\comp2021

4.    Start the ISE Project Navigator and select the New Project... option (under the File menu) to create a new project in E:\comp2021 called lab03c. You should see the following screen before clicking on OK.

 

5.    Right click on the xcv50-6bg256-XST VHDL entry of the 'Sources in Project' box in the top-left panel of the Project Navigator and choose the ‘VHDL Module’ option within the dialog box. Enter the filename codeconv for this design. Your screen should look like the following. Proceed by clicking ‘Next’ until you hit Finish. The tool provides a stub for a VHDL design but we will not be using that for this part of the lab, so delete everything in the file for now.

 

6.    Copy and paste the attached codeconv.vhd source into the screen. The inserted code should appear similar to the screen snapshot below. The source file consists of a template for the structural description of a 84-2-1 to BCD code converter. The structural description makes use of gate components that have also been described within the source file using a behavioral coding style. More typically, these gates would be defined externally in a shared library package.

7.    Modify the code by inserting your structural circuit descriptions for the X, Y, and Z output bits. Note: it may be desirable, and it is allowable, that one of these be specified using a behavioral style.

8.    In order to simulate the design, you will first need to create a simulator test bench for your code. Right click on the xcv50-6bg256-XST VHDL entry again, and select New Source.... This time, select Test Bench Waveform and give it a meaningful name, such as test3c. Associate the test bench with the source codeconv. After you click finish, the HDL bencher should start and you will see this screen.

The code converter is a combinatorial design, and the default values are reasonable, so click OK. You will then see this screen.

 

9.    The HDL converter parses the code converter module and extracts the input and output signals of interest. In order to thoroughly test your design, it is necessary to set up representative stimulator signals for the inputs. A systematic way to do so is to set the input signals so that they toggle between 0 and 1 at different frequencies. To set up such a signal, double click on the leftmost blue patch of one of the input signals, say d; a button denoted Pattern should pop up, click on it to start the Pattern Wizard as in the following figure.

 

10.    Choose the toggle pattern. Since d is the least significant bit of the input signal, it is reasonable to toggle it every step, so leave the Toggle Every entry at 1. There are 4 signals so there are 24=16 combinations of input values, and repeating the pattern 8 times is sufficient. For the other input signals, it is necessary to change the 'Toggle Every' and 'Repeat pattern # times' entries to appropriate values.

When you have finished defining the test bench waveform, click on Save Waveform. When you save a waveform for the first time, HDL Bencher will ask you how many cycles after the last input assignment should the test bench end. The default value is fine. Exit the HDL Bencher after you have finished.

11.    You are now ready to simulate your design. Click on the test3c.tbw entry that you have just created. Observe that the 'Processes for Current Source' box in the lower left hand corner changes to the process for a test bench. Double click on 'Simulate Behavioral VHDL Model' to start the ModelSim simulator and verify your design.

It is possible that the Modelsim simulator will detect errors in your Code Converter design and fail. When that happens, it will typically give meaningful error messages for you to track down errors in your code. Simply close Modelsim and rerun the above step after you have corrected the errors.

If your code contains no syntatic errors a screen similar to the figure below will appear.

 

12.    We are interested in the wave window. Maximise that window and set the zoom range from 0 ps to 16 ns.

Check carefully over an entire period of the A signal that the output is as expected. Use the truth table provided in Section A2 above as a verification aid. If there are any discrepancies, try to identify the problem by backtracking: check that your circuit implementation is as designed on paper, then check that your paper design is correct. If you identify a design flaw, modify your circuit description, save the file, check its syntax, re-synthesise, and re-simulate.

13.    Save your simulation waveforms to a file by selecting Print Postscript... from the File menu of the wave window. You will need to modify the print options to save the postscript output to the E: that you have mapped. Give the postscript file a meaningful name such as E:\comp2021\lab03c\codeconv.ps. This will produce a postscript file that can be viewed with postscript viewers and laser printed using the Unix lpr command.

 

C.Main Task

To perform the main task, you will need to take the following steps. You will have to record the outcome of every step and present them to your demonstrator for marking. The VHDL codes, block diagrams, simulation reports and all other design related documents must be presented together.

 

 1.   Review the design of the full adder/subtractor in lab 2.

 2.   Study the principle of decoders.

 3.   Find the logical equations for the active-low 2-to-4-line decoder with enable provided in the following logic diagram, and truth table:

        

 4.   Construct a behavioral (dataflow) model for the above decoder, in VHDL language.

 5.   Construct a structural model for an active-low 3-to-8-line decoder (without enable input) , using the behavioral model defined above as a component.

       Hint:

a.   Use two of the 2-to-4-line decoders with enable and an inverter to implement the 3-to-8-line decoder without an enable input.

b.  Draw a block diagram of your 3-to-8-line decoder showing it's internal structure.

        6.   Use the structural model defined above, to design a mixed (structural and behavioral) model for a 1-bit full-adder.


  1. Draw the truth table for a 1-bit full-adder with inputs Ai  and Bi, and carry-in line Ci. The output is Si and the carry-out Ci+1.

  2. Derive product of max-term expressions for Ci+1 and Si.

  3. Using the signal names nD0 to nD7 to identify the outputs of the 3-to-8-line decoder, provide VHDL concurrent signal assignment statements for Ci+1 and Si.

7.   Build and test a 4-bit ripple-carry adder with Cin/Cout.

            Hint: A 4-bit ripple-carry adder is constructed from four full-adders FA0-FA3 by wiring the carry-out of each full-adder to the next significant carry-in.

 

 

8.   Using the model defined in step 7 above, build and test a mixed model for a 4-bit adder/subtracter using XOR functions to perform the conditional complementation. Use the signal as the add/subtract control signal.

        a.  Draw the block diagram for your adder/subtracter, illustrating the internal structure.

        b.  Provide the structutal model for XOR function, on the B input.