Circuit-level simulations predict increased vulnerability of flip-flop designs and increased occurrence of single-event upsets in advanced technologies due to ...

Upset trends in flip-flop designs at deep submicron technologies . Benakanakere Sheshadri, Vijay (2010-09-08). Department: Electrical Engineering. Advances in ...

Single-node upsets (SNUs), as well as double-node upsets (DNUs), are typical soft errors. This paper proposes two radiation-hardened FF designs, namely DNU- ...

Abstract—Circuit-level simulations predict increased vulnerability of flip-flop designs and increased occurrence of single-event upsets in advanced ...

nodes to establish SE trends in flip-flop designs. This work begins with a literary survey of various SE phenomena that cause flip-flop SEUs in hardened and ...

Circuit-level simulations predict increased vulnerability of flip-flop designs and increased occurrence of single-event upsets in advanced technologies due ...

The desire to make technology faster, smaller and more affordable compels us to shrink transistors further. As we realize designs with millions of ...

This paper presents a new single event upset tolerant flip-flop design by applying the hardening technique on DICE at the layout level. This approach is an ...

In this paper, four upsets in 17 years of satellite operation were observed in bipolar J-K flip-flops operating in a communications satellite. The authors used ...